1. Field of the Invention
The present invention relates to a multi thread processor that has a reconfigurable logic circuit, and in particular to technology for switching threads.
2. Description of the Related Art
Processors in recent years, for example, processors mounted on audio-visual apparatuses that use digital signals, perform multi-threaded processing in order to perform a plurality of processes in parallel.
Meanwhile, devices that change a logical configuration with use of a program, such as a FPGA (Field Programmable Gate Array) and a PLD (Programmable Logic Device), have been developed. Furthermore, dynamic reconfigurable logic circuits that can change the configuration at high speed have been proposed.
A technique for performing multi-threaded processing has been developed (see Patent Document 1), with use of dynamic reconfigurable logic circuits that satisfy both the flexibility of such software processing and high-speed performance of hardware processing.
The following briefly describes the above-noted technique with reference to FIG. 33.
The multi-threaded processing is performed by a multi thread processor 10 together with a dynamic reconfigurable operation circuit 20.
When interrupted by the multi thread processor 10, which gives an instruction to switch threads, the dynamic reconfigurable operation circuit 20 reconfigures the configuration, namely (i) the configuration of operation cells 21 that are arranged in array and (ii) the configuration of a connection between the operation cells, for a thread to be executed next, and executes the next thread.
When switching threads, each operation cell 21 saves, in an intermediate operation data storing unit register 211 thereof, the result of an operation performed in a current thread, and then performs reconfiguration.
With the above-described technique, all operation cells are reconfigured for the next threads, without the result of the operations of each operation cell being destroyed when switching threads, and without the multi thread processor 10 waiting until the operations of all the operation cells have completed. Therefore, it is possible to shorten the time required for the multi thread processor 10 to start the operation of the next thread, which has an advantageous effect of reducing the degradation of the operation performance.    [Patent Document 1] Japanese Laid-Open Patent Application No. 2005-165961.